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1 ltc1408 1408fa 6 channel, 14-bit, 600ksps simultaneous sampling adc with shutdown the ltc ? 1408 is a 14-bit, 600ksps adc with six simulta- neously sampled differential inputs. the device draws only 5ma from a single 3v supply, and comes in a tiny 32 pin (5mm 5mm) qfn package. a sleep shutdown feature lowers power consumption to 6 w. the combina- tion of low power and tiny package makes the ltc1408 suitable for portable applications. the ltc1408 contains six separate differential inputs that are sampled simultaneously on the rising edge of the conv signal. these six sampled inputs are then converted at a rate of 100ksps per channel. the 90db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the device converts 0v to 2.5v unipolar inputs differen- tially, or 1.25v bipolar inputs also differentially, depending on the state of the bip pin. any analog input may swing rail-to-rail as long as the differential input range is maintained. the conversion sequence can be abbreviated to convert fewer than six channels, depending on the logic state of the sel2, sel1 and sel0 inputs. the serial interface sends out the six conversion results in 96 clocks for compatibility with standard serial interfaces. 600ksps adc with 6 simultaneously sampled differential inputs 100ksps throughput per channel 76db sinad low power dissipation: 15mw 3v single supply operation 2.5v internal bandgap reference, can be overdriven with external reference 3-wire serial interface internal conversion triggered by conv sleep (6 w) shutdown mode nap (3.3mw) shutdown mode 0v to 2.5v unipolar, or 1.25v bipolar differential input range 90db common mode rejection tiny 32-pin (5mm 5mm) qfn package multiphase power measurement multiphase motor control data acquisition systems uninterruptable power supplies applicatio s u features descriptio u block diagra w , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6084440, 6522187. C + 4 5 25 24 C + 7 6 9 12 13 16 19 8 ch0 C ch0 + ch1 C ch1 + 10 11 C + 14 15 ch2 C ch2 + ch3 C ch3 + C + 17 18 C + 20 21 s and h s and h s and h s and h s and h ch4 C ch4 + ch5 C ch5 + mux v ref 10 f bip sel2 sel1 sel0 gnd 2.5v reference 600ksps 14-bit adc 14-bit latch 5 14-bit latch 4 14-bit latch 3 14-bit latch 2 14-bit latch 1 14-bit latch 0 10 f3v v cc v dd 26 29 23 22 33 27 28 2 1 sd0 0.1 f 3 ov dd 3v 32 sck 31 dgnd ognd 30 conv three- state serial output port timing logic 1408 ta01 C + s and h
2 ltc1408 1408fa a u g w a w u w a r b s o lu t exi t i s (notes 1, 2) supply voltage (v dd , v cc , ov dd ) .............................. 4v analog input voltage (note 3) ................................... C 0.3v to (v dd + 0.3v) digital input voltage .................... C 0.3v to (v dd + 0.3v) digital output voltage .................. C 0.3v to (v dd + 0.3v) power dissipation .............................................. 100mw operation temperature range ltc1408c ............................................... 0 c to 70 c ltc1408i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 125 c the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference, v dd = 3v, v dd = v cc = 3v. parameter conditions min typ max units resolution (no missing codes) 14 bits integral linearity error (note 5) C3 0.5 3 lsb offset error (note 4) C4.5 1 4.5 mv offset match from ch0 to ch5 C3 0.5 3 mv range error (note 4) C12 212 mv range match from ch0 to ch5 C5 15 mv range tempco internal reference (note 4) 15 ppm/ c external reference 1 ppm/ c the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference, v dd = 3v, v dd = v cc = 3v. symbol parameter conditions min typ max units v in analog differential input range (notes 3, 8, 9) 2.7v v dd 3.3v 0 to 2.5 v v cm analog common mode + differential 0 to v dd v input range (note 8) i in analog input leakage current 1 a c in analog input capacitance 13 pf t acq sample-and-hold acquisition time (note 6) 39 ns t ap sample-and-hold aperture delay time 1 ns t jitter sample-and-hold aperture delay time jitter 0.3 ps t sk channel to channel aperture skew 200 ps cmrr analog input common mode rejection ratio f in = 100khz, v in = 0v to 3v C83 db f in = 10mhz, v in = 0v to 3v C67 db co verter characteristics u a alog i put u u wu u package / o rder i for atio order part number qfn part marking t jmax = 125 c, ja = 34 c/ w exposed pin is gnd (pad 33) must be soldered to pcb consult ltc marketing for parts specified with wider operating temperature ranges. 16 15 14 13 12 11 10 9 25 26 27 28 top view qfn package 32-pin (5mm 5mm) plastic qfn 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 ch4 + ch4 C gnd ch5 + ch5 C gnd v ref v cc ch1 C ch1 + gnd ch0 C ch0 + ov dd ognd sdo gnd ch3 C ch3 + gnd gnd ch2 C ch2 + gnd v dd sel2 sel1 sel0 bip conv dgnd sck 33 ltc1408cuh ltc1408iuh 1408 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
3 ltc1408 1408fa i ter al refere ce characteristics uu u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference, v dd = 3v, v dd = v cc = 3v. symbol parameter conditions min typ max units sinad signal-to-noise plus 100khz input signal 73 76 db distortion ratio 300khz input signal 76 db 100khz input signal, external v ref = 3.3v, v dd 3.3v 79 db 300khz input signal, external v ref = 3.3v, v dd 3.3v 79 db thd total harmonic 100khz first 5 harmonics C80 C90 db distortion 300khz first 5 harmonics C86 db sfdr spurious free 100khz input signal 90 db dynamic range 300khz input signal 86 db imd intermodulation 0.625v p-p , 833khz into ch0+, 0.625v p-p , 841khz into ch0C. C80 db distortion bipolar mode. also applicable to other channels code-to-code v ref = 2.5v (note 17) 0.7 lsb rms transition noise full power bandwidth v in = 2.5v p-p , sdo = 11585lsb p-p (C3dbfs) (note 15) 50 mhz full linear bandwidth s/(n + d) 68db, bipolar differential input 5 mhz t a = 25 c. v dd = v cc = 3v. parameter conditions min typ max units v ref output voltage i out = 0 2.5 v v ref output tempco 15 ppm/ c v ref line regulation v dd = 2.7v to 3.6v, v ref = 2.5v 600 v/v v ref output resistance load current = 0.5ma 0.2 ? v ref settling time 2ms the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = v cc = 3v. symbol parameter conditions min typ max units v ih high level input voltage v dd = 3.3v 2.4 v v il low level input voltage v dd = 2.7v 0.6 v i in digital input current v in = 0v to v dd 10 a c in digital input capacitance 5pf v oh high level output voltage v dd = 3v, i out = C 200 a 2.5 2.9 v v ol low level output voltage v dd = 2.7v, i out = 160 a 0.05 v v dd = 2.7v, i out = 1.6ma 0.4 v i oz hi-z output leakage d out v out = 0v and v dd 10 a c oz hi-z output capacitance d out 1pf i source output short-circuit source current v out = 0v, v dd = 3v 20 ma i sink output short-circuit sink current v out = v dd = 3v 15 ma dy a ic accuracy u w digital i puts a d digital outputs u u
4 ltc1408 1408fa symbol parameter conditions min typ max units f sample(max) maximum sampling frequency per channel 100 khz (conversion rate) t throughput minimum sampling period (conversion + acquisiton period) 667 ns t sck clock period (note 16) 100 10000 ns t conv conversion time (notes 6, 17) 96 sclk cycles t 1 minimum positive or negative sclk pulse width (note 6) 2 ns t 2 conv to sck setup time (notes 6, 10) 3 10000 ns t 3 sck before conv (note 6) 0 ns t 4 minimum positive or negative conv pulse width (note 6) 4 ns t 5 sck to sample mode (note 6) 4 ns t 6 conv to hold mode (notes 6, 11) 1.2 ns t 7 96th sck to conv interval (affects acquisition period) (notes 6, 7, 13) 45 ns t 8 minimum delay from sck to valid bits 0 through 11 (notes 6, 12) 8 ns t 9 sck to hi-z at sdo (notes 6, 12) 6 ns t 10 previous sdo bit remains valid after sck (notes 6, 12) 2 ns t 11 v ref settling time after sleep-to-wake transition (notes 6, 14) 2 ms the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. with internal reference, v dd = v cc = 3v. symbol parameter conditions min typ max units v dd , v cc supply voltage 2.7 3.6 v i dd + i cc supply current active mode, f sample = 600ksps 57 ma nap mode 1.1 1.9 ma sleep mode 2.0 15 a pd power dissipation active mode with sck, f sample = 600ksps 15 mw power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v dd = 3v. ti i g characteristics u w note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliabilty and lifetime. note 2: all voltage values are with respect to ground gnd. note 3: when these pins are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below gnd or greater than v dd without latchup. note 4: offset and range specifications apply for a single-ended ch0 + C ch5 + input with ch0 C C ch5 C grounded and using the internal 2.5v reference. note 5: integral linearity is tested with an external 2.55v reference and is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. the deviation is measured from the center of quantization band. linearity is tested for ch0 only. note 6: guaranteed by design, not subject to test. note 7: recommended operating conditions. note 8: the analog input range is defined for the voltage difference between chx + and chx C , x = 0C5. note 9: the absolute voltage at chx + and chx C must be within this range. note 10: if less than 3ns is allowed, the output data will appear one clock cycle later. it is best for conv to rise half a clock before sck, when running the clock at rated speed. note 11: not the same as aperture delay. aperture delay (1ns) is the difference between the 2.2ns delay through the sample-and-hold and the 1.2ns conv to hold mode delay. note 12: the rising edge of sck is guaranteed to catch the data coming out into a storage latch. note 13: the time period for acquiring the input signal is started by the 96th rising clock and it is ended by the rising edge of conv. note 14: the internal reference settles in 2ms after it wakes up from sleep mode with one or more cycles at sck and a 10 f capacitive load. note 15: the full power bandwidth is the frequency where the output code swing drops by 3db with a 2.5v p-p input sine wave. note 16: maximum clock period guarantees analog performance during conversion. output data can be read with an arbitrarily long clock period. note 17: the conversion process takes 16 clocks for each channel that is enabled, up to 96 clocks for all 6 channels.
5 ltc1408 1408fa sinad, enobs vs frequency sfdr vs input frequency v dd = 3v, t a = 25 c thd, 2nd and 3rd vs input frequency typical perfor a ce characteristics uw 98khz unipolar sine wave 4096 point fft plot, 100 ksps 98khz bipolar sine wave 4096 point fft plot, 100 ksps snr vs input frequency thd, 2nd and 3rd vs input frequency frequency (mhz) 56 sinad (db) enobs (bits) 59 62 65 68 71 74 77 1 10 100 1408 g01 53 9 9.5 10 10.5 11 11.5 12 12.5 8.5 0.1 unipolar single ended bipolar differential frequency (mhz) C98 thd (db) C92 C74 C80 C86 C68 C62 C56 C50 C44 1 10 100 1408 g02 C104 0.1 5 harmonic thd unipolar single ended 2nd 3rd frequency (mhz) C98 thd (db) C92 C74 C80 C86 C68 C62 C56 C50 C44 1 10 100 1408 g03 C104 0.1 5 harmonic thd bipolar single ended v cm = 1.5v 2nd 3rd frequency (mhz) 50 sfdr (db) 56 74 68 62 80 86 92 98 104 1 10 100 1408 g04 44 0.1 unipolar single ended bipolar differential frequency (mhz) 65 snr (db) 66 69 68 67 70 71 72 75 74 73 76 1 10 100 1408 g05 64 0.1 unipolar single ended bipolar differential frequency(khz) 0 C120 output magnitude (db) C80 C90 C100 C110 C40 C60 C70 C50 0 C10 C20 C30 10 30 20 1408 g06 40 50 frequency(khz) 0 C120 output magnitude (db) C80 C90 C100 C110 C40 C60 C70 C50 0 C10 C20 C30 10 30 20 1408 g07 40 50 591khz bipolar differential sine wave 4096 point fft plot, 100 ksps 101khz unipolar single ended sine wave 4096 point fft plot, 625 ksps frequency(khz) 0 C120 output magnitude (db) C80 C90 C100 C110 C40 C60 C70 C50 0 C10 C20 C30 10 30 20 1408 g08 40 50 frequency(khz) 0 C120 output magnitude (db) C80 C90 C100 C110 C40 C60 C70 C50 0 C10 C20 C30 62.5 188 125 1408 g09 250 313
6 ltc1408 1408fa 610khz unipolar single ended input sine wave 4096 point fft, 625ksps 833khz into ch0 +, 841khz into ch0 ? 588ksps bipolar mode 4096 point fft full scale signal response integral linearity end point fit differential linearity for ch0 with internal 2.5v reference, unipolar mode integral linearity end point fit for ch0 with internal 2.5v reference, unipolar mode v dd = 3v, t a = 25 c typical perfor a ce characteristics uw frequency(khz) 0 C120 output magnitude (db) C80 C90 C100 C110 C40 C60 C70 C50 0 C10 C20 C30 62.5 188 125 1408 g10 250 313 frequency(khz) 0 C120 magnitude (db) C80 C90 C100 C110 C40 C60 C70 C50 0 C10 C20 C30 50 150 100 1408 g11 200 250 300 1408 g12 output code 0 C1.0 differential linearity (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 4096 8192 C0.6 0.6 0.8 0.2 12288 16384 output code 0 C4.0 integral linearity (lsb) C3.2 C1.6 C0.8 0 4.0 1.6 4096 8192 1408 g13 C2.4 2.4 3.2 0.8 12288 16384 output code 0 C1.0 differential linearity (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 4096 8192 1408 g14 C0.6 0.6 0.8 0.2 12288 16384 differential linearity for ch0 with internal 2.5v reference, differential input in bipolar mode output code 0 C4.0 integral linearity (lsb) C3.2 C1.6 C0.8 0 4.0 1.6 4096 8192 1408 g15 C2.4 2.4 3.2 0.8 12288 16384 frequency (mhz) C24 C27 magnitude (db) C21 C12 C15 C18 C9 C6 C3 0 3 100 1000 1408 g16 C30 10 1408 g20 frequency (hz) C100 cmrr (db) C60 C20 C40 C80 0 10k 100k 1m 10m 100m 1g C120 100 1k 1408 g21 frequency (hz) C100 pssr (db) C60 C20 C40 C80 0 10k 100k 1m 10m 100m 1g C120 100 1k crosstalk vs frequency cmrr vs frequency
7 ltc1408 1408fa uu u pi fu ctio s sdo (pin 1): three-state serial data output. each set of six output data words represent the six analog input channels at the start of the previous conversion. data for ch0 comes out first and data for ch5 comes out last. each data word comes out msb first. ognd (pin 2): ground return for sdo currents. this pad must always be within 300mv of the ground plane poten- tial. ov dd (pin 3): power supply for the sdo pin. ov dd must be no more than 300mv higher than v dd and can be brought to a lower voltage to interface to low voltage logic families. the unloaded high state at sdo is at the potential of ov dd . ch0 + (pin 4): non-inverting channel 0. ch0 + operates fully differentially with respect to ch0 C with a 0v to 2.5v, or 1.25v differential swing and a 0v to v dd absolute input range. ch0 (pin 5): inverting channel 0. ch0 C operates fully differentially with respect to ch0 + with a C2.5v to 0v, or 1.25v differential swing and a 0v to v dd absolute input range. gnd (pins 6, 9, 12, 13, 16, 19): analog grounds. these ground pins must be tied directly to the solid ground plane under the part. analog signal currents flow through these connections. ch1 + (pin 7): non-inverting channel 1. ch1 + operates fully differentially with respect to ch1 C with a 0v to 2.5v, or 1.25v differential swing and a 0v to v dd absolute input range. ch1 (pin 8): inverting channel 1. ch1 C operates fully differentially with respect to ch1 + with a C2.5v to 0v, or 1.25v differential swing and a 0v to v dd absolute input range. ch2 + (pin 10): non-inverting channel 2. ch2 + operates fully differentially with respect to ch2 C with a 0v to 2.5v, or 1.25v differential swing and a 0v to v dd absolute input range. ch2 (pin 11): inverting channel 2. ch2 C operates fully differentially with respect to ch2 + with a C2.5v to 0v, or 1.25v differential swing and a 0v to v dd absolute input range. v dd = 3v, t a = 25 c typical perfor a ce characteristics uw time (ns) C5 output code 6144 8192 10240 10 20 1408 g22 4096 2048 0 05 15 12288 14336 16384 25 ch0 thru ch5 rising ch0 thru ch5 falling 1408 g23 frequency (hz) C100 cmrr (db) C60 C20 C40 C80 0 10k 100k 1m 10m 100m 1g C120 100 1k simultaneous step at all 6 channels from 25 ? source sampling frequency = 625ksps input frequency = 625.0381mhz psrr vs frequency
8 ltc1408 1408fa ch3 + (pin 14): non-inverting channel 3. ch3 + operates fully differentially with respect to ch3 C with a 0v to 2.5v, or 1.25v differential swing and a 0v to v dd absolute input range. ch3 (pin 15): inverting channel 3. ch3 C operates fully differentially with respect to ch3 + with a C2.5v to 0v, or 1.25v differential swing and a 0v to v dd absolute input range. ch4 + (pin 17): non-inverting channel 4. ch4 + operates fully differentially with respect to ch4 C with a 0v to 2.5v, or 1.25v differential swing and a 0v to v dd absolute input range. ch4 (pin 18): inverting channel 4. ch4 C operates fully differentially with respect to ch4 + with a C2.5v to 0v, or 1.25v differential swing and a 0v to v dd absolute input range. ch5 + (pin 20): non-inverting channel 5. ch5 + operates fully differentially with respect to ch5 C with a 0v to 2.5v, or 1.25v differential swing and a 0v to v dd absolute input range. ch5 (pin 21): inverting channel 5. ch5 C operates fully differentially with respect to ch5 + with a C2.5v to 0v, or 1.25v differential swing and a 0v to v dd absolute input range. gnd (pin 22): analog ground for reference. analog ground must be tied directly to the solid ground plane under the part. analog signal currents flow through this connection. the 10 f reference bypass capacitor should be returned to this pad. v ref (pin 23): 2.5v internal reference. bypass to gnd and a solid analog ground plane with a 10 f ceramic capacitor (or 10 f tantalum in parallel with 0.1 f ce- ramic). can be overdriven by an external reference voltage between 2.55% and v dd , v cc . v cc (pin 24): 3v positive analog supply. this pin supplies 3v to the analog section. bypass to the solid analog ground plane with a 10 f ceramic capacitor (or 10 f tantalum) in parallel with 0.1 f ceramic. care should be taken to place the 0.1 f bypass capacitor as close to pin 24 as possible. pin 24 must be tied to pin 25. v dd (pin 25): 3v positive digital supply. this pin supplies 3v to the logic section. bypass to dgnd pin and solid analog ground plane with a 10 f ceramic capacitor (or 10 f tantalum in parallel with 0.1 f ceramic). keep in mind that internal digital output signal currents flow through this pin. care should be taken to place the 0.1 f bypass capacitor as close to pin 25 as possible. pin 25 must be tied to pin 24. sel2 (pin 26): most significant bit controlling the number of channels being converted. in combination with sel1 and sel0, 000 selects just the first channel (ch0) for conversion. incrementing selx selects additional channels(ch0Cch5) for conversion. 101, 110 or 111 select all 6 channels for conversion. must be kept in a fixed state during conversion and during the subsequent con- version to read data. sel1 (pin 27): middle significance bit controlling the number of channels being converted. in combination with sel0 and sel2, 000 selects just the first channel (ch0) for conversion. incrementing selx selects additional channels for conversion. 101, 110 or 111 select all 6 channels (ch0Cch5) for conversion. must be kept in a fixed state during conversion and during the subsequent conversion to read data. sel0 (pin 28): least significant bit controlling the number of channels being converted. in combination with sel1 and sel2, 000 selects just the first channel (ch0) for conversion. incrementing selx selects additional channels for conversion. 101, 110 or 111 select all 6 channels (ch0Cch5) for conversion. must be kept in a fixed state during conversion and during the subsequent conversion to read data. bip (pin 29): bipolar/unipolar mode. the input differen- tial range is 0v C 2.5v when bip is low, and it is 1.25 when bip is high. must be kept in fixed state during conversion and during subsequent conversion to read data. when changing bip between conversions the full acquisition time must be allowed before starting the next conversion. the output data is in 2s complement format for bipolar mode and straight binary format for unipolar mode. uu u pi fu ctio s
9 ltc1408 1408fa block diagra w 2 ognd 1 sd0 3 ov dd 3v C + 4 5 24 23 s & h C + 7 6 9 12 13 16 19 8 s & h gnd exposed pad v ref 10 f ch0 C ch0 + ch1 C ch1 + C + 10 11 s & h C + 14 15 s & h ch2 C ch2 + ch3 C ch3 + C + 17 18 s & h C + 20 21 s & h ch4 C ch4 + ch5 C ch5 + 10 f 0.1 f ltc1408 dgnd 32 sck 30 conv sel2 sel1 sel0 three- state serial output port mux 2.5v reference timing logic v cc 25 3v v dd 1408 bd 600ksps 14-bit adc 14-bit latch 5 14-bit latch 4 14-bit latch 3 14-bit latch 2 14-bit latch 1 14-bit latch 0 26 27 bip 29 28 31 22 33 0.1 f conv (pin 30): convert start. holds the six analog input signals and starts the conversion on the rising edge. two pulses with sck in fixed high or fixed low state starts nap mode. four or more pulses with sck in fixed high or fixed low state starts sleep mode. dgnd (pin 31): digital ground. this ground pin must be tied directly to the solid ground plane. digital input signal currents flow through this pin. sck (pin 32): external clock input. advances the conver- sion process and sequences the output data at sd0 (pin1) on the rising edge. one or more pulses wake from sleep or nap power saving modes. 16 clock cycles are needed for each of the channels that are activated by selx (pins 26, 27, 28), up to a total of 96 clock cycles needed to convert and read out all 6 channels. exposed pad (pin 33): gnd. must be tied directly to the solid ground plane. uu u pi fu ctio s
10 ltc1408 1408fa ltc1408 timing diagram ti i g diagra s w u w
11 ltc1408 1408fa nap mode and sleep mode waveforms sck to sdo delay t 8 t 10 sck sdo 1408 td03 v ih v oh v ol t 9 sck sdo hi-z v ih sck conv nap sleep v ref t 1 t 11 t 1 note: nap and sleep are internal signals 1408 td02 ti i g diagra s w u w
12 ltc1408 1408fa applicatio s i for atio wu uu select number of converted channels (sel2, sel1, sel0) these three control pins select the number of channels being converted. 000 selects only the first channel (ch0) for conversion. incrementing selx selects additional chan- nels for conversion, up to 6 channels. 101, 110 or 111 select all 6 channels for conversion. these pins must be kept in a fixed state during conversion and during the subsequent conversion to read data. when changing modes between conversions, keep in mind that the output data of a particular channel will remain unchanged until after that channel is converted again. for example: convert a sequence of 4 channels (ch0, ch1, ch2, ch3) with selx = 011, then, after these channels are converted change selx to 001 to convert just ch0 and ch1. see table 1. during the conversion of the first set of two channels you will be able to read the data from the same two channels converted as part of the previous group of 4 channels. later, you could convert 4 or more channels to read back the unread ch2 and ch3 data that was converted in the first set of 4 channels. these pins are often hardwired to enable the right number of channels for a particular application. bipolar/unipolar mode the input voltage range for each of the chx input differen- tial pairs is unipolar 0v C 2.5v when bip is low, and bipolar 1.25v when bip is high. this pin must be kept in fixed state during conversion and during subsequent conversion to read data. when changing bip between conversions the full acquisition time must be allowed before starting the next conversion. after changing modes from bipolar to unipolar, or from unipolar to bipolar, you can still read the first set of channels in the new mode, by inverting the msb to read these channels in the mode that they were converted in. driving the analog input the differential analog inputs of the ltc1408 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the ch0 C input is grounded). all twelve analog inputs of all six differential analog input pairs, ch0 + with ch0 C , ch1 + with ch1 C , ch2 + with ch2 C , ch3 + with ch3 C , ch4 + with ch4 C and ch5 + with ch5 C , are sampled at the same instant. any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejection of the sample-and-hold circuit. the inputs draw only one small current spike while charg- ing the sample-and-hold capacitors at the end of conver- sion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc1408 inputs can be driven directly. as source impedance increases, so will acquisition time. for minimum acquisition time with high source impedance, a buffer amplifier must be used. the main requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (the time allowed for settling must be at least 39ns for full throughput rate). also keep in mind, while choosing an input amplifier, the amount of noise and harmonic distortion added by the amplifier. table 1. conversion sequence control (?cquire?represents simultaneous sampling of all channels; chx represents conversion of channels) sel2 sel1 sel0 channel acquisition and conversion sequence 0 0 0 acquire, ch0, acquire, ch0... 0 0 1 acquire, ch0, ch1, acquire, ch0, ch1... 0 1 0 acquire, ch0, ch1, ch2, acquire, ch0, ch1, ch2... 0 1 1 acquire, ch0, ch1, ch2, ch3, acquire, ch0, ch1, ch2, ch3... 1 0 0 acquire, ch0, ch1, ch2, ch3, ch4, acquire, ch0,ch1,ch2, ch3, ch4... 1 0 1 acquire, ch0, ch1, ch2, ch3, ch4, ch5, acquire, ch0, ch1, ch2, ch3, ch4, ch5... 1 1 0 acquire, ch0, ch1, ch2, ch3, ch4, ch5, acquire, ch0, ch1, ch2, ch3, ch4, ch5... 1 1 1 acquire, ch0, ch1, ch2, ch3, ch4, ch5, acquire, ch0, ch1, ch2, ch3, ch4, ch5...
13 ltc1408 1408fa ltc1566-1: low noise 2.3mhz continuous time lowpass filter. lt 1630: dual 30mhz rail-to-rail voltage fb amplifier. 2.7v to 15v supplies. very high a vol , 500 v offset and 520ns settling to 0.5lsb for a 4v swing. thd and noise are C 93db to 40khz and below 1lsb to 320khz (a v = 1, 2v p-p into 1k ? , v s = 5v), making the part excellent for ac applications (to 1/3 nyquist) where rail-to-rail perfor- mance is desired. quad version is available as lt1631. lt1632: dual 45mhz rail-to-rail voltage fb amplifier. 2.7v to 15v supplies. very high a vol , 1.5mv offset and 400ns settling to 0.5lsb for a 4v swing. it is suitable for applications with a single 5v supply. thd and noise are C 93db to 40khz and below 1lsb to 800khz (a v = 1, 2v p-p into 1k ? , v s = 5v), making the part excellent for ac applications where rail-to-rail performance is desired. quad version is available as lt1633. lt1801: 80mhz gbwp, C75dbc at 500khz, 2ma/ampli- fier, 8.5nv/ hz. lt1806/lt1807: 325mhz gbwp, C80dbc distortion at 5mhz, unity gain stable, rail-to-rail in and out, 10ma/amplifier, 3.5nv/ hz. lt1810: 180mhz gbwp, C90dbc distortion at 5mhz, unity gain stable, rail-to-rail in and out, 15ma/amplifier, 16nv/ hz. lt1818/lt1819: 400mhz, 2500v/ s, 9ma, single/dual voltage mode operational amplifier. lt6200: 165mhz gbwp, C85dbc distortion at 1mhz, unity gain stable, rail-to-rail in and out, 15ma/amplifier, 0.95nv/ hz. lt6203: 100mhz gbwp, C80dbc distortion at 1mhz, unity gain stable, rail-to-rail in and out, 3ma/amplifier, 1.9nv/ hz. lt6600: amplifier/filter differential in/out with 10mhz cutoff. choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100 ? ) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100 ? . the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small- signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1408 depends on the application. generally, applications fall into two catego- ries: ac applications where dynamic specifications are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1408. (more detailed information is avail- able in the linear technology databooks and on the website at www.linear.com.) applicatio s i for atio wu uu linearview is a trademark of linear technology corporation.
14 ltc1408 1408fa applicatio s i for atio wu uu input filtering and source impedance the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1408 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 50mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 1 shows a 47pf capacitor from cho + to ground and a 51 ? source resistor to limit the net input bandwidth to 30mhz. the 47pf ca- pacitor also acts as a charge reservoir for the input sample- and-hold and isolates the adc input from sampling-glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distor- tion. npo and silvermica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency a multiple pole filter is required. high external source resistance, combined with 13pf of input capacitance, will reduce the rated 50mhz input band- width and increase acquisition time beyond 39ns. input range the analog inputs of the ltc1408 may be driven fully differentially with a single supply. either input may swing up to v cc , provided the differential swing is no greater than 2.5v with bip (pin 29) low, or 1.25v with (bip pin 29) high. the 0v to 2.5v range is also ideally suited for single- ended input use with single supply applications. the common mode range of the inputs extend from ground to the supply voltage v cc . if the difference between the ch + and ch C at any input pair exceeds 2.5v (unipolar) or 1.25v (bipolar), the output code will stay fixed at positive full- scale, and if this difference goes below 0v (unipolar) or C 1.25v (bipolar), the output code will stay fixed at negative full-scale. internal reference the ltc1408 has an on-chip, temperature compensated, bandgap reference that is factory trimmed near 2.5v to obtain a precise 2.5v input span. the reference amplifier output v ref , (pin 23) must be bypassed with a capacitor to ground. the reference amplifier is stable with capaci- tors of 1 f or greater. for the best noise performance, a 10 f ceramic or a 10 f tantalum in parallel with a 0.1 f ceramic is recommended. the v ref pin can be overdriven with an external reference as shown in figure 2. the volt- age of the external reference must be higher than the 2.5v of the open-drain p-channel output of the internal refer- ence. the recommended range for an external reference is 2.55v to v dd . an external reference at 2.55v will see a dc quiescent load of 0.75ma and as much as 3ma figure 1. rc input filter ltc1408 ch0 + ch0 C v ref gnd 1408 f01 1 2 11 3 10 f 47pf* 51 ? * ch1 + ch1 C 4 5 47pf* *tight tolerance required to avoid aperture skew degradation 51 ? * analog input analog input figure 2. external reference ltc1408 v ref gnd 1408 f02 23 22 10 f 3v ref
15 ltc1408 1408fa applicatio s i for atio wu uu figure 4 shows the ideal input/output characteristics for the ltc1408 in unipolar mode (bip = low). the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, fs C 1.5lsb). the output code is straight binary with 1lsb = 2.5v/16384 = 153 v for the ltc1408. the ltc1408 has 0.7 lsb rms of gaussian white noise. during conversion. input span versus reference voltage the differential input range has a unipolar voltage span that equals the difference between the voltage at the reference buffer output v ref (pin 23) and the voltage at ground. the differential input range of the adc is 0v to 2.5v when using the internal reference. the internal adc is referenced to these two nodes. this relationship also holds true with an external reference. differential inputs the adc will always convert the difference of ch + minus ch C , independent of the common mode voltage at any pair of inputs. the common mode rejection holds up at high frequencies (see figure 3.) the only requirement is that both inputs not go below ground or exceed v dd . figure 3. cmrr vs frequency 1408 g20 frequency (hz) C100 cmrr (db) C60 C20 C40 C80 0 10k 100k 1m 10m 100m 1g C120 100 1k integral nonlinearity errors (inl) and differential nonlin- earity errors (dnl) are largely independent of the common mode voltage. however, the offset error will vary. dc cmrr is typically better than C90db. figure 5 shows the ideal input/output characteristics for the ltc1408 in bipolar mode (bip = high). the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, fs C 1.5lsb). the output code is 2s complement with 1lsb = 2.5v/16384 = 153 v for the ltc1408. the ltc1408 has 0.7 lsb rms of gaussian white noise. figure 5. ltc1408 transfer characteristic in bipolar mode (bip = high) input voltage (v) 2's complement output code 1408 f05 011...111 011...110 011...101 100...000 100...001 100...010 fs ?1lsb ?s figure 4. ltc1408 transfer characteristic in unipolar mode (bip = low) input voltage (v) straight binary output code 1408 f04 111...111 111...110 111...101 000...000 000...001 000...010 fs C 1lsb 0
16 ltc1408 1408fa applicatio s i for atio wu uu power-down modes upon power-up, the ltc1408 is initialized to the active state and is ready for conversion. the nap and sleep mode waveforms show the power down modes for the ltc1408. the sck and conv inputs control the power down modes (see timing diagrams). two rising edges at conv, with- out any intervening rising edges at sck, put the ltc1408 in nap mode and the power drain drops from 15mw to 3.3mw. the internal reference remains powered in nap mode. one or more rising edges at sck wake up the ltc1408 for service very quickly and conv can start an accurate conversion within a clock cycle. four rising edges at conv, without any intervening rising edges at sck, put the ltc1408 in sleep mode and the power drain drops from 15mw to 10 w. one or more rising edges at sck wake up the ltc1408 for operation. the internal reference (v ref ) takes 2ms to slew and settle with a 10 f load. using sleep mode more frequently compromises the accuracy of the output data. note that for slower conver- sion rates, the nap and sleep modes can be used for substantial reductions in power consumption. digital interface the ltc1408 has a 3-wire spi (serial peripheral interface) interface. the sck and conv inputs and sdo output implement this interface. the sck and conv inputs accept swings from 3v logic and are ttl compatible, if the logic swing does not exceed v dd . a detailed description of the three serial port signals follows: conversion start input (conv) the rising edge of conv starts a conversion, but subse- quent rising edges at conv are ignored by the ltc1408 until the following 96 sck rising edges have occurred. the duty cycle of conv can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. a simple approach to generate conv is to create a pulse that is one sck wide to drive the ltc1408 and then buffer this signal to drive the frame sync input of the processor serial port. it is good practice to drive the ltc1408 conv input first to avoid digital noise interference during the sample-to- hold transition triggered by conv at the start of conver- sion. it is also good practice to keep the width of the low portion of the conv signal greater than 15ns to avoid introducing glitches in the front end of the adc just before the sample-and-hold goes into hold mode at the rising edge of conv.
17 ltc1408 1408fa applicatio s i for atio wu uu minimizing jitter on the conv input in high speed applications where high amplitude sinewaves above 100khz are sampled, the conv signal must have as little jitter as possible (10ps or less). the square wave output of a common crystal clock module usually meets this requirement easily. the challenge is to generate a conv signal from this crystal clock without jitter corrup- tion from other digital circuits in the system. a clock divider and any gates in the signal path from the crystal clock to the conv input should not share the same integrated circuit with other parts of the system. the sck and conv inputs should be driven first, with digital buffers used to drive the serial port interface. also note that the master clock in the dsp may already be corrupted with jitter, even if it comes directly from the dsp crystal. another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10mhz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40mhz). the jitter in these pll-generated high speed clocks can be several nanoseconds. note that if you choose to use the frame sync signal generated by the dsp port, this signal will have the same jitter of the dsps master clock. the typical application figure on page 20 shows a circuit for level-shifting and squaring the output from an rf signal generator or other low-jitter source. a single d-type flip flop is used to generate the conv signal to the ltc1408. re-timing the master clock signal eliminates clock jitter introduced by the controlling device (dsp, fpga, etc.) both the inverter and flip flop must be treated as analog components and should be powered from a clean analog supply. serial clock input (sck) the rising edge of sck advances the conversion process and also udpates each bit in the sdo data stream. after conv rises, the third rising edge of sck sends out up to six sets of 14 data bits, with the msb sent first. a simple approach is to generate sck to drive the ltc1408 first and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. use the falling edge of the clock to latch data from the serial data output (sdo) into your processor serial port. the 14-bit serial data will be received right justified, in six 16-bit words with 96 or more clocks per frame sync. if fewer than 6 channels are selected by sel0Csel2 for conversion, then 16 clocks are needed per channel to convert the analog inputs and read out the resulting data after the next convert pulse. it is good practice to drive the ltc1408 sck input first to avoid digital noise interference during the internal bit compari- son decision by the internal high speed comparator. unlike the conv input, the sck input is not sensitive to jitter because the input signal is already sampled and held constant. serial data output (sdo) upon power-up, the sdo output is automatically reset to the high impedance state. the sdo output remains in high impedance until a new conversion is started. sdo sends out up to six sets of 14 bits in the output data stream after the third rising edge of sck after the start of conversion with the rising edge of conv. the six or fewer 14-bit words are separated by two clock cycles in high impedance mode. please note the delay specifica- tion from sck to a valid sdo. sdo is always guaranteed to be valid by the next rising edge of sck. the 16 C 96- bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors.
18 ltc1408 1408fa applicatio s i for atio wu uu 1408 f06 3 30 32 1 2 3-wire serial interface link ov dd conv sck ltc1408 sdo v cc bfsr bclkr tms320c54x bdr ognd 31 dgnd conv 0v to 3v logic swing clk 5v 3v b13 b12 figure 7. dsp serial interface to tms320c54x board layout and bypassing wire wrap boards are not recommended for high resolu- tion and/or high speed a/d converters. to obtain the best performance from the ltc1408, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track. if optimum phase match between the inputs is desired, the length of the twelve input wires of the six input channels should be kept matched. but each pair of input wires to the six input channels should be kept separated by a ground trace to avoid high frequency crosstalk between channels. high quality tantalum and ceramic bypass capacitors should be used at the v cc , v dd and v ref pins as shown in the block diagram on the first page of this data sheet. for optimum performance, a 10 f surface mount tantalum capacitor with a 0.1 f ceramic is recommended for the v cc , v dd and v ref pins. alternatively, 10 f ceramic chip capacitors such as x5r or x7r may be used. the capacitors must be lo- cated as close to the pins as possible. the traces connect- ing the pins and the bypass capacitors must be kept short and should be made as wide as possible. the v cc and v dd bypass capacitor returns to the ground plane and the v ref bypass capacitor returns to the pin 22. care should be taken to place the 0.1 f v cc and v dd bypass capacitor as close to pins 24 and 25 as possible. figure 6. recommended layout figure 6 shows the recommended system ground connec- tions. all analog circuitry grounds should be terminated at the ltc1408 exposed pad. the ground return from the ltc1408 to the power supply should be low impedance for noise-free operation. the exposed pad of the 32-pin qfn package is also internally tied to the ground pads. the exposed pad should be soldered on the pc board to reduce ground connection inductance. all ground pins (gnd, dgnd, ognd) must be connected directly to the same ground plane under the ltc1408. v dd bypass, 0.1 f, 0402 ov dd bypass, 0.1 f, 0402 v ref bypass, 10 f, 0805 v cc bypass, 0.1 f, 0402 and 10 f, 0805 hardware interface to tms320c54x the ltc1408 is a serial output adc whose interface has been designed for high speed buffered serial ports in fast digital signal processors (dsps). figure 7 shows an example of this interface using a tms320c54x. the buffered serial port in the tms320c54x has direct access to a 2kb segment of memory. the adcs serial data can be collected in two alternating 1kb segments, in real time, at the full 600ksps conversion rate of the ltc1408. the dsp assembly code sets frame sync mode at the bfsr pin to accept an external positive going pulse and the serial clock at the bclkr pin to accept an external positive edge clock. buffers near the ltc1408 may be added to drive long tracks to the dsp to prevent corruption of the signal to ltc1408. this configuration is adequate to traverse a typical system board, but source resistors at the buffer outputs and termination resistors at the dsp, may be needed to match the characteristic impedance of very long transmission lines. if you need to terminate the sdo transmission line, buffer it first with one or two 74acxx gates. the ttl threshold inputs of the dsp port respond properly to the 3v swing used with the ltc1408.
19 ltc1408 1408fa u package descriptio information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom viewexposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 1004 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 0.05 3.45 0.05 (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout pin 1 notch r = 0.30 typ or 0.35 45 chamfer uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693)
20 ltc1408 1408fa related parts ? linear technology corporation 2006 lt 0606 ? printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com part number description comments adcs ltc1402 12-bit, 2.2msps serial adc 5v or 5v supply, 4.096v or 2.5v span ltc1403/ltc1403a 12-/14-bit, 2.8msps serial adc 3v, 15mw, unipolar inputs, msop package ltc1403-1/ltc1403a-1 12-/14-bit, 2.8msps serial adc 3v, 15mw, bipolar inputs, msop package ltc1405 12-bit, 5msps parallel adc 5v, selectable spans, 115mw ltc1407/ltc1407a 12-/14-bit, 3msps simultaneous sampling adc 3v, 14mw, 2-channel unipolar input range ltc1407-1/ltc1407a-1 12-/14-bit, 3msps simultaneous sampling adc 3v, 14mw, 2-channel bipolar input range ltc1411 14-bit, 2.5msps parallel adc 5v, selectable spans, 80db sinad ltc1412 12-bit, 3msps parallel adc 5v supply, 2.5v span, 72db sinad ltc1420 12-bit, 10msps parallel adc 5v, selectable spans, 72db sinad ltc1608 16-bit, 500ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1609 16-bit, 250ksps serial adc 5v configurable bipolar/unipolar inputs ltc1864/ltc1865 16-bit, 250ksps 1-/2-channel serial adcs 5v or 3v (l-version), micropower, msop package ltc1864l/ltc1865l dacs ltc1592 16-bit, serial softspan tm i out dac 1lsb inl/dnl, software selectable spans ltc1666/ltc1667 12-/14-/16-bit, 50msps dac 87db sfdr, 20ns settling time ltc1668 references lt1460-2.5 micropower series voltage reference 0.10% initial accuracy, 10ppm drift lt1461-2.5 precision voltage reference 0.04% initial accuracy, 3ppm drift lt1790-2.5 micropower series reference in sot-23 0.05% initial accuracy, 10ppm drift softspan is a trademark of linear technology corporation. u typical applicatio pre v cc 1k 1k 50 ? v cc nl17sz74 convert enable nc7svu04p5x master clock 0.1 f to ltc1408 conv control logic (fpga, cpld, dsp, etc.) dq q clr 1408 ta02 clock squaring/level shifting circuit allows testing with rf sine generator. convert re-timing flip-flop preserves low-jitter clock timing

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